Novel field effect transistor and method of fabrication

ABSTRACT

The present invention is a novel field effect transistor having a channel region formed from a narrow bandgap semiconductor film formed on an insulating substrate. A gate dielectric layer is formed on the narrow bandgap semiconductor film. A gate electrode is then formed on the gate dielectric. A pair of source/drain regions formed from a wide bandgap semiconductor film or a metal is formed on opposite sides of the gate electrode and adjacent to the low bandgap semiconductor film.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to the field of semiconductorintegrated circuits and more specifically to a depleted substratetransistor (DST) and its method of fabrication.

[0003] 2. Discussion of Related Art

[0004] Modern integrated circuits today are made up of literallyhundreds of millions of transistors integrated together into functionalcircuits. In order to further increase the computational power of logicintegrated circuits, the density and performance of the transistors mustbe further increased and the operating voltage (Vcc) further reduced. Inorder to increase device performance and reduce operating voltages,silicon on insulator (SOI) transistors have been proposed for thefabrication of modern integrated circuits. Fully depleted SOItransistors have been proposed as transistor structure to take advantageof the ideal subthreshold gradients for optimized on current/off currentratios. That is, an advantage of SOI transistors is that they experiencelower leakage currents thereby enabling lower operating voltage for thetransistor. Lowering the operating voltage of the transistor enables lowpower, high performance integrated circuits to be fabricated. FIG. 1illustrates a standard fully depleted silicon on insulator (SOI)transistor 100. SOI transistor 100 includes a single crystalline siliconsubstrate 102 having an insulating layer 104, such as buried oxideformed thereon. A single crystalline silicon body 106 is formed on theinsulating layer 104. A gate dielectric layer 108 is formed on a singlecrystalline silicon body 106 and a gate electrode 110 formed on gatedielectric 108. Source 112 and drain 114 regions are formed in thesilicon body 106 along laterally opposite sides of the gate electrode110. Unfortunately, the amount of gate oxide scaling and gate lengthscaling that can be reliably and uniformly achieved with today'sstructures and processes is becoming limited.

[0005] Thus, what is desired is a novel transistor structure whichenables further Vcc scaling and improved electrical performance.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006]FIG. 1 is an illustration of a cross-sectional view of a siliconon insulator (SOI) transistor.

[0007]FIG. 2 is an illustration of a cross-sectional view of a fieldeffect transistor in accordance with the present invention.

[0008] FIGS. 3A-3G illustrates a method of forming a field effecttransistor in accordance with embodiments of the present invention.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

[0009] The present invention is a novel field effect transistor and itsmethod of fabrication. In the following description numerous specificdetails have been set forth in order to provide a thorough understandingof the present invention. However, one of ordinary skill in the art,will realize that the invention may be practiced without theseparticular details. In other instances, well-known semiconductorequipment and processes have not been described in particular detail soas to avoid unnecessarily obscuring the present invention.

[0010] The present invention is a novel field effect transistor and itsmethod of fabrication. The transistor of the present invention has anultra high channel mobility formed from a narrow bandgap semiconductor,such as InSb. Because a channel is formed from a narrow bandgap material(less than 0.7 eV at room temperature) it has a high channel mobilityand saturation velocity which results in more drive current for lowervoltages. Large drive current with low voltages enables a transistor tobe operated at low operating voltages, such as less than 0.5 volt. Thetransistor can be formed on an insulating substrate so that a depletedsubstrate transistor (DST) can be formed. The use of an insulatingsubstrate prevents leakage of junction charge into the substrate. Thesource and drain regions of the transistor can be specially engineeredto help prevent or reduce leakage currents associated with narrowbandgap materials. In one embodiment of the present invention, thesource/drain regions are formed from a metal, such as platinum,aluminum, and gold which can form a “Schottky” barrier with the narrowbandgap semiconductor film used to form the channel region so that abarrier to change injection is formed. In another embodiment of thepresent invention, the source and drain regions can be formed from awide bandgap semiconductor film, such as InAlSb, GaP and GaSb. The useof a large bandgap semiconductor in the source/drain region (and specialbandedge engineering between the source/drain semiconductor and channelregion semiconductor), next to narrow bandgap channel region reduces theleakage current of the device. The use of special band engineeredsource/drain regions and an insulating substrate helps minimize thelarge junction leakage current associated with narrow bandgap materials.

[0011] A field effect transistor 200 in accordance with an embodiment ofthe present invention is illustrated in FIG. 2. Field effect transistor200 is formed on an insulating substrate 202. In an embodiment of thepresent invention, insulating substrate 202 includes an insulating film204 grown on a substrate 206. In other embodiments, other types ofinsulating substrates, such as but not limited to hafium oxide,zirconium oxide, and barium titanate (BaTiO₃) may be used.

[0012] Transistor 200 includes a channel region 208 formed from a narrowbandgap, less than 0.5 eV, semiconductor film formed on insulatingsubstrate 202. In an embodiment of the present invention, the channelregion is formed from an InSb (Bandgap=0.17 eV) compound. In otherembodiments, the channel region is formed with a PdTe (Bandgap=0.31 eV)or InAs (Bandgap=0.36 eV) compound film. In an embodiment of the presentinvention, the InSb compound is doped with n type impurities, such asarsenic, antinomy and phosphorous to a level between 1×10¹⁷-1×10¹⁸atoms/cm² to fabricate a p type device. In another embodiment of thepresent invention, the channel region 208 is doped with p typeimpurities, such as boron to a level between 1×10¹⁷-1×10¹⁸ atoms/cm² tofabricate a n type device. In another embodiment of the presentinvention, the channel region 208 is an undoped or intrinsicsemiconductor film having a narrow bandgap. In an embodiment of thepresent invention, the channel region is formed to a thickness ofapproximately ⅓ the gate length (L_(g)) of the device. Utilizing a thinfilm, less than 10 nanometers, enables a fully depleted substratetransistor (DST) to be formed with Lg of 30 nm. The use of a narrowbandgap channel region enables ultra high mobility and saturationvelocities and hence high performance and low Vcc for logicapplications.

[0013] Transistor 200 has a gate dielectric 210 formed on the thin filmchannel region 208. Although the gate dielectric 210 can be a growndielectric, such as SiO₂ or silicon oxynitride, the gate dielectric ispreferably a deposited dielectric so that is can be formed at lowertemperatures, less than 500° C., and thereby be compatible with thenarrow bandgap channel region film (e.g., InSb). In an embodiment of thepresent invention, the gate dielectric 210 is or includes a highdielectric constant film. A high dielectric constant film has adielectric constant of greater than 9.0 and ideally greater than 50. Ahigh dielectric constant film can be a metal oxide dielectric, such asbut not limited to tantalum pentaoxide (Ta₂O₅), titanium oxide, hefiumoxide, zirconium oxide, and aluminum oxide. The gate dielectric layer210, however, can be other well known high dielectric constant films,such as lead zirconate titanate (PZT) or barium strontium titatanate(BST). Utilizing a high dielectric constant film enables a gatedielectric to be formed relatively thick between 20-3000 Å and ideallyabout 200 Å for a high dielectric constant (k>100) material. A thickgate dielectric layer helps block gate leakage current of the device.Any well known techniques, such as vapor deposition or sputtering can beused to deposit gate dielectric film 210. In an embodiment of thepresent invention, a low temperature process, between 200-500° C., isused to deposit the gate dielectric.

[0014] Transistor 200 includes a gate electrode 212 formed on a gatedielectric 210. In an embodiment of the present invention, gateelectrode 212 is a metal gate electrode, such as but not limited totungsten (W), tantalum (Ta), titanium (Ti) and their silicides andnitrides. In an embodiment of the present invention, the gate electrodeis formed from a film having a work function between n type silicon andp type silicon, such as a work function between 4.1 eV and 5.2 eV. In anembodiment of the present invention, the gate electrode is formed of ametal or film having a midgap work function. A metal gate electrode isdesirable when a metal oxide dielectric is used because they arecompatible with metal oxide dielectrics and can be directly formedthereon. Gate electrode 212 has a pair of laterally opposite sidewalls214 and 216 which run along the gate width of the device. The distancebetween the laterally opposite sidewalls defines the gate length (L_(g))of the device. In an embodiment of the present invention, the gateelectrode 212 is formed with a gate length of 300 nanometers or less.The gate width (G_(w)) of the transistor is the distance the gateelectrode extends over the channel region in a direction perpendicularto the gate length (i.e., into and out of the page of FIG. 2). Gateelectrode 212 need not necessarily be made of a single film, but may bemade from multiple films to form a composite gate electrode which mayinclude, for example a metal film, silicon films, and suicides. When ametal oxide dielectric is used a metal film should be formed directly onthe metal oxide dielectric. In an embodiment of the present invention,gate electrode 212 is formed to a thickness between 500-1000 Å. In anembodiment of the present invention, gate electrode 212 is formedutilizing a low temperature less than 500° C. and preferably less than350° C., process such as sputtering.

[0015] Transistor 200 includes a source region 220 and drain region 222.The source region 220 and drain region 222 are formed on insulatingsubstrate 202 as shown in FIG. 2. The source region 220 and drain region222 extend into and out of the page of FIG. 2 along the laterallyopposite sidewalls 214 and 216 of gate electrode 212. Gate electrode 212on gate dielectric 210 slightly overlaps the source region 220 and thedrain region 222 as shown in FIG. 2. Ideally, the overlap is less thanapproximately 10% of the gate length on each side. The source region 220is separated from the drain region 222 by a channel region 208 as shownin FIG. 2.

[0016] In an embodiment of the present invention, the source region 220and the drain region 222 are formed of materials which surpressparasitic transistor leakage due to the low bandgap of the channelregion. In an embodiment of the present invention, the source region 220and drain regions 222 are formed from a wide or high bandgapsemiconductor material. When forming the source 220 and drain 222 regionfrom a semiconductor material, the band gap of the semiconductor film ofthe source 220 and drain 222 regions should have a bandgap which isgreater than the bandgap of the channel region. In an embodiment, thebandgap of the source and drain semiconductor material is at least 0.2eV and ideally at least 0.5 eV greater than the bandgap of thesemiconductor film 208 in the channel region. The bandgap offset betweenthe source/drain semiconductor 220 and 222 film and the channelsemiconductor film 208 prevents carrier injection over the barrier. Inan embodiment of the present invention, the source region 220 and drainregion 222 are formed from a III-V compound semiconductor having alarger band gap compared to the channel region semiconductor, such asbut not limited to InP (Bandgap=1.35 eV), GaSb (Bandgap=0.75 eV), GaP,and GaAs (Bandgap=1.43). However, other semiconductor materials, such asgermanium (Bandgap=0.67 eV) having a suitably large bandgap can be used.The source/drain semiconductor film can be a polycrystalline film or asingle crystalline film. The semiconductor film 220 and 222 can be dopedto a concentration level between 1×10²⁰-1×10²¹ atoms/cm³ with n typeimpurities, such as arsenic, antimony or phosphorous in order to form an type MOS device (NMOS) and can be doped to a concentration levelbetween 1×10²⁰-1×10²¹ atoms/cm² with p type impurities, such as boron orgallium when forming a p type device (PMOS). By forming the source 220and drain 222 regions with a wide or large bandgap material and placingthem next to the narrow or small bandgap channel region 208 a barrier iscreated which suppresses parasitic transistor leakage which wouldnormally occur with a low bandgap channel region.

[0017] In another embodiment of the present invention, the source regionand drain regions are formed from a metal film. In an embodiment of thepresent invention, the source and drain regions are formed from a metalor film (“Schottky metal”), such as but not limited to platinum (Pf),aluminum (Al) and gold (Au) which can form a “Schottky” barrier with thesemiconductor film of the channel region 208. The “Schottky” barrierwhich is created by placing the metal source and drain regions incontact with the semiconductor film of the channel region forms abarrier to electric flow from the source and drain regions into thechannel region. In this way, a bias is needed in order to injectcarriers from the source 220 and drain 222 into the channel 208. In anembodiment of the present invention, the source region and drain regionsare formed from a metal film, such as but not limited to titaniumnitride (TiN), tantalum nitride (TaN) and hefium nitride (HfN).

[0018] The use of an insulating substrate and special band engineeredsource/drain regions surpresses parasitic transistor leakage due to thelow bandgap of the channel region material (e.g., InSb). In this way,transistor 200 can function as a low power, high performance device.

[0019] Transistor 200 can be operated in a fully depleted manner whereinwhen transistor 200 is turned “ON” the channel region 208 fully depletesthereby providing the advantageous electrical characteristics andperformance of a fully depleted substrate transistor (DST). That is,when transistor 200 is turned “ON” an inversion layer at the surface ofregion 208 is formed that has the same conductivity type as the sourceand drain regions and forms a conductive channel between the source anddrain regions to allow current to flow there between. A depletion regionwhich is depleted of free carriers is formed beneath the inversionlayer. The depletion region extends to the bottom of channel region 208,thus, the transistor can be said to be a “fully depleted” transistor.Fully depleted transistors have improved electrical performancecharacteristics over non-fully depleted or partially depletedtransistors. For example, operating transistor 200 in a fully depletedmanner, gives transistor 200 an ideal or very sharp subthreshold slope.Additionally, by operating transistor 200 in a fully depleted manner,transistor 200 has improved drain induced barrier (dibble) loweringwhich provides for better “OFF” state leakage which results in lowerleakage and thereby lower power consumption. In order to operatetransistor 200 in a fully depleted manner, the thickness of channelregion 208 is ideally ⅓ of the gate length (L_(g)) of the transistor.

[0020] FIGS. 3A-3G illustrate a method of forming the field effecttransistor 200 in accordance with an embodiment of the presentinvention. Fabrication of field effect transistor in accordance with thepresent invention begins with an insulating substrate 300 having anarrow bandgap semiconductor film, such as InSb formed thereon. In anembodiment of the present invention, the substrate is an insulatingsubstrate 300 such as shown in FIG. 3A. In an embodiment of the presentinvention, insulating substrate 300 includes a lower monocrystallinesilicon substrate 302 and a top insulating layer 304, such as a silicondioxide film, metal oxide or silicon nitride film. Insulating layer 304isolates narrow bandgap semiconductor material 306 from substrate 302and in an embodiment is formed to a thickness between 200-2000 Å.Isolating or insulating layer 304 is sometimes referred to as a “buriedoxide” layer. Substrate 302 can be a semiconductor substrate, such asbut not limited to a silicon monocrystalline substrate and othersemiconductor substrate.

[0021] Narrow bandgap semiconductor film 306 can be formed on insulatingsubstrate 300 with any suitable method. For example, narrow bandgapsemiconductor film 306 can be formed onto an insulating substrate 300utilizing a transfer process. In this technique, first a silicon waferhas a thin oxide grown on its surface that will later serve as thebarrier oxide 304. Next, a high dose hydrogen implant is made into anarrow bandgap semiconductor film substrate to form a high stress regionbelow the surface of the narrow bandgap semiconductor substrate. Thenarrow bandgap semiconductor wafer is then flipped over and bonded tothe surface of the oxide 304 layer formed on the silicon substrate 302.The narrow bandgap semiconductor substrate is then cleaved along thehigh stress region created by the hydrogen implant. This results in astructure with a thin low bandgap semiconductor film 306 formed on topof the buried oxide film 304 which in turn is formed or on top of thesingle crystalline substrate 302. Well known smoothing techniques, suchas HCl smoothing or chemical mechanical polishing can be used to smooththe top surface of the low bandgap semiconductor film 306 to its desiresthickness. In an embodiment of the present invention, the semiconductorfilm 306 is an intrinsic (i.e., undoped) narrow bandgap semiconductorfilm. In other embodiments, narrow bandgap semiconductor film 306 isdoped to a p type or n type conductivity with a concentration levelbetween 1×10⁶-1×10¹⁹ atoms/cm³. Semiconductor film 306 can be insitudoped (i.e., doped while it is deposited) or doped after it is formed onsubstrate 300, for example, by ion implantation 307. Doping afterformation enables both PMOS and NMOS devices to be fabricated easily onthe same insulating substrate 300. The doping level of the narrowbandgap semiconductor material determines the doping level of thechannel region of the device.

[0022] Next, as shown in FIG. 3B, a photoresist mask 308 is formed onnarrow bandgap semiconductor material 306. Photoresist mask 308 can beformed by well known technique, such as by masking, exposing anddeveloping a blanket deposited photoresist film. The photoresist mask308 covers the portion of low bandgap semiconductor material 306 whichis to become the channel region of the transistor. After formingphotoresist layer 308, the narrow bandgap semiconductor film 306 isanisotropically etched in alignment with the photoresist mask utilizingwell known techniques to completely remove the narrow bandgapsemiconductor material 306 from locations 312 and 314 on oxide 304 wherethe source and drain regions are to subsequently be formed. Afteretching the narrow bandgap semiconductor material the portion of thenarrow bandgap semiconductor material that remains provides the channelregion for the transistor.

[0023] Next, as shown in FIG. 3C, the photoresist mask 308 is removedwith well known techniques and a film 316 used to form the source anddrain regions blanket deposited over substrate 300. In an embodiment ofthe present invention, film 316 is a large or wide bandgap semiconductormaterial, such as a III-V compound semiconductor, such as but notlimited to InAlSb, InP, GaSb, GaP, and GaAs. In another embodiment ofthe present invention, the source/drain material 316 is formed from ametal, such as platinum, aluminum and gold which forms a Schottkybarrier with narrow bandgap material 306. It is to be appreciated thatthe source/drain material 316 is formed in contact with the sidewall ofthe narrow bandgap semiconductor material 306 as shown in FIG. 3C. Thesource/drain film 316 is ideally blanket deposited by a low temperature,less than 500 C, process such as sputtering or molecular beam epitaxy.The source/drain film 316 will typically be deposited to a thickness atleast as thick as the narrow bandgap semiconductor film 306.

[0024] Next, as shown in FIG. 3D, source/drain film 316 is planarized sothat it becomes substantially planar with the top surface of narrowbandgap semiconductor material 306. Source/drain film 316 can beplanarized with well known techniques, such as but not limited tochemical mechanical polishing and plasma etch back.

[0025] Next, as shown in FIG. 3E, a gate dielectric layer 318 is formedon narrow bandgap semiconductor film 306. Gate dielectric layer 318 isideally a deposited dielectric film. In an embodiment of the presentinvention, gate dielectric layer 318 is a high dielectric constantdielectric film, such as a metal oxide dielectric as described above. Adeposited dielectric will blanket deposit over all surfaces of substrate300 including the narrow bandgap semiconductor film 306 and film 316used to form the source and drain regions. Any well known technique,such as vapor deposition or sputtering can be used to deposit gatedielectric 318. In an embodiment of the present invention, a lowtemperature process, between 200-500° C., is used to deposit gatedielectric layer 318. Gate dielectric layer 318 can be formed to athickness between 20-3000 Å and ideally between about 20-200 Å.

[0026] Next, as shown in FIG. 3F, a gate electrode film or films 320 areblanket deposited over gate dielectric layer 318. Gate electrode film320 is ideally a metal film, such as tungsten, titanium and tantalum andtheir silicides and nitrides as set forth above. A photoresist mask 322is then formed with well known techniques, such as masking, exposing anddeveloping to define locations where the gate electrode of the device isto be formed. The photoresist mask 322 is formed over and completelycovers the patterned narrow bandgap semiconductor material 306 used toform the channel region of the device. The photoresist mask can be madeslightly wider than the narrow bandgap semiconductor channel region 306in order to ensure complete gate coverage of the channel region and toaccount for misalignment.

[0027] Next, as shown in FIG. 3G, the gate electrode film 320 is etchedin alignment with photoresist mask 322 to define a gate electrode 320for the device. The gate electrode completely covers the patternednarrow bandgap semiconductor film used to form the channel of thedevice. Additionally, at this time, the gate oxide layer formed on thesource and drain regions 316 can be removed also. Next, if desired, suchas when a wide bandgap semiconductor material is used as film 316 toform the source and drain regions, a source/drain implant 324 can beutilized to dope the source and drain regions 316 to the desiredconductivity type and concentration. This completes the fabrication of afield effect transistor having a channel region formed from a narrowbandgap semiconductor film and specially engineered source and drainregions which prevent undesired carrier injection into the channel.

[0028] Thus, a novel transistor having a high channel mobility andsaturation velocity which can be operated at low operating voltages,such as less than 0.7 Vcc, has been described.

We claim:
 1. A transistor comprising: a channel region formed from anarrow bandgap semiconductor film formed on insulating substrate; a gatedielectric formed on said low bandgap semiconductor film; a gateelectrode formed on said gate dielectric; and a pair of source/drainregions formed from a semiconductor film having a wider bandgap thansaid low bandgap semiconductor film formed on opposite sides of saidgate electrode and adjacent to said low bandgap semiconductor film. 2.The transistor of claim 1 wherein said narrow bandgap semiconductor filmhas a bandgap of less than or equal to 0.7 eV.
 3. The transistor ofclaim 1 wherein said narrow bandgap semiconductor film comprises InSb.4. The transistor of claim 2 wherein said low bandgap semiconductor filmis selected from the group consisting of InAs, PdTe and InSb.
 5. Thetransistor of claim 1 wherein said gate dielectric comprises a highdielectric constant film.
 6. The transistor of claim 1 wherein saidsource and drain regions are formed from a III-V semiconductor.
 7. Thetransistor of claim 1 wherein said gate electrode is a metal gateelectrode.
 8. The transistor of claim 1 wherein the bandgap of saidsemiconductor film of said source/drain regions is at least 0.2 eVgreater than the bandgap of said channel region.
 9. The transistor ofclaim 1 wherein said semiconductor film of said source/drain regions isselected from the group consisting of InAlSb, InP, GaSb, GaP, and GaAs.10. A transistor comprising: a channel region formed from narrow bandgapsemiconductor film formed on an insulating substrate; a gate dielectricformed on said narrow bandgap semiconductor film; a gate electrodeformed on said gate dielectric; and a pair of metal source/drain regionsformed along opposite sides of said gate electrode and adjacent to saidnarrow bandgap semiconductor film.
 11. The transistor of claim 10wherein said low bandgap semiconductor film has a bandgap of less thanor equal to 0.7 eV.
 12. The transistor of claim 10 wherein said lowbandgap semiconductor film is selected from the group consisting ofInAs, PdTe and InSb.
 13. The transistor of claim 10 wherein saidsource/drain regions are formed from a material selected from the groupconsisting of titanium nitride, tantalum nitride and hefium nitride. 14.The transistor of claim 10 wherein said source/drain regions are formedfrom a metal film which can form a Schottky barrier with said lowbandgap semiconductor film.
 15. The transistor of claim 10 wherein saidmetal film is selected from the group consisting of platinum, aluminumand gold.
 16. The transistor of claim 10 wherein said gate dielectrichas a dielectric constant greater than 9.0.
 17. The transistor of claim10 wherein said gate dielectric comprises a metal oxide dielectric. 18.The transistor of claim 10 wherein said gate dielectric layer isselected from the group consisting of PZT, BST, tantalum pentaoxide,hefium oxide, zirconium oxide and aluminum oxide.
 19. The transistor ofclaim 10 wherein said gate dielectric layer has a thickness between20-3000 Å.
 20. The transistor of claim 10 wherein said gate electrodecomprises a metal film.
 21. The transistor of claim 10 wherein said gateelectrode has a midgap work function.
 22. The transistor of claim 10wherein said transistor has a gate length of less than or equal to 30nanometers.
 23. The transistor of claim 10 wherein said thickness ofsaid low bandgap semiconductor film is approximately ⅓ the gate lengthof said transistor.
 24. The transistor of claim 10 wherein saidinsulating substrate comprises a silicon dioxide film formed on amonocyrstalline silicon substrate.
 25. A transistor comprising: an InSballoy film formed on an oxide film formed on a monocrystalline siliconsubstrate; a gate dielectric layer formed on said InSb alloy filmwherein said gate dielectric is a high dielectric constant film; a metalgate electrode formed on said gate dielectric layer; and a source regionand a drain regions formed on opposite sides of said gate electrodeadjacent to said InSb alloy film and on said oxide film, said source anddrain regions formed from a metal film.
 26. The transistor of claim 25wherein said metal film is selected from a material which can form aSchottky barrier with said InSb alloy.
 27. The transistor of claim 25wherein said metal film is selected from the group consisting oftitanium nitride, tantalum nitride and hefium nitride.
 28. A transistorcomprising: an InSb alloy film formed on an oxide film formed on amonocrystalline silicon substrate; a gate dielectric layer formed onsaid InSb alloy film wherein said gate dielectric is a high dielectricconstant film; a metal gate electrode formed on said gate dielectriclayer; and a source region and a drain regions formed on opposite sidesof said gate electrode adjacent to said InSb alloy film and on saidoxide film, said source and drain regions formed from a semiconductorfilm having a wide bandgap.
 29. The transistor of claim 28 wherein saidsemiconductor film is selected from the group consisting of InP, GaSb,GaP, and GaAs.
 30. The transistor of claim 28 wherein said gatedielectric is selected from the group consisting of PZT, BST, tantalumpentaoxide, hefium oxide, zirconium oxide and aluminum oxide.
 31. Amethod of forming a transistor comprising: forming a narrow bandgapsemiconductor film on an insulating substrate; forming a gate dielectriclayer on said narrow bandgap semiconductor film; forming a gateelectrode on said gate dielectric; and forming a pair of source/drainregions adjacent to said narrow bandgap semiconductor film.
 32. Themethod of claim 31 wherein said narrow bandgap semiconductor film has abandgap of less than or equal to 0.7 eV.
 33. The method of claim 32wherein said narrow bandgap semiconductor film is selected groupconsisting of InAs, PdTe and InSb.
 34. The method of claim 32 whereinsaid source/drain regions are formed from a semiconductor film having alarger bandgap then said narrow bandgap semicomductor film.
 35. Themethod of claim 31 wherein said source/drain regions are formed from acompound semiconductor.
 36. The method of claims 34 wherein saidsemiconductor film of said source/drain regions is selected from thegroup consisting of InAlSb, InP,GaSb, GaP, and GaAs.
 37. The method ofclaim 31 wherein said source/drain regions are formed from a metal film.38. The method of claim 37 wherein said metal film forms a Schottkybarrier with said narrow bandgap semiconductor film.
 39. The method ofclaim 37 wherein said metal film is selected from the group consistingof titanium nitride, tantalum nitride and hefium nitride.
 40. The methodof clam 31 wherein said gate dielectric layer comprises a deposited highdielectric constant film.
 41. The method of claim 31 wherein said gateelectrode comprises a metal film.
 42. A method of forming a transistorcomprising: forming an InSb alloy film on an insulating substrate;forming a high dielectric constant gate dielectric film on said InSballoy film; forming a metal gate electrode on said gate dielectriclayer; and forming a pair of source/drain regions on opposite sides ofsaid gate electrode on said insulating substrate.
 43. The method ofclaim 42 wherein said source/drain regions are formed from a metal film.44. The method of claim 42 wherein said source/drain regions are formedfrom a wide bandgap semiconductor film.
 45. A transistor comprising: achannel region formed from a narrow bandgap semiconductor film formed oninsulating substrate; a gate dielectric formed on said narrow bandgapsemiconductor film; a gate electrode formed on said gate dielectric; anda pair of source/drain regions formed on said insulating substrate andadjacent to opposite sides of said narrow bandgap semiconductor film.46. The transistor of claim 45 wherein said source/drain regions areformed from a metal film.
 47. The transistor of claim 45 wherein saidsource/drain regions are formed from a wide bandgap semiconductor film.